// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "01/29/2019 17:02:20"
                                                                                
// Verilog Test Bench template for design : flow_led
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ns
module flow_led_tb();
// constants                                           
// general purpose registers
// reg eachvec;
// test vector input registers
reg sys_clk;
reg sys_rst_n;
// wires                                               
wire [3:0]  led;

// assign statements (if any)                          
flow_led i1 (
// port map - connection between master ports and signals/registers   
	.led(led),
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n)
);
initial                                                
begin                                                  
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    #100 sys_rst_n = 1'b1;
//    #1000 $stop;
end                                                    
always  #10 sys_clk = ~sys_clk;                                                 
                                           
                                                
endmodule

